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Cache memory
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#	Item
281	Toward Predictable Performance in Software Packet-Processing Platforms Mihai Dobrescu EPFL, Switzerland Katerina Argyraki Add to Reading List Source URL: www.eecs.berkeley.edu Language: English - Date: 2012-11-24 04:26:29 Microprocessors CPU cache Central processing unit Computer memory Electronics Multi-core processor Packet Processing Xeon Transmission Control Protocol Computing Computer hardware Cache
282	Algorithmic Improvements for Fast Concurrent Cuckoo Hashing Add to Reading List Source URL: www.pdl.cmu.edu Language: English - Date: 2014-10-22 17:34:26 Computer architecture Remote direct memory access Dynamic random-access memory Computer data storage CPU cache Cache Random-access memory Lustre Memory bandwidth Computer memory Computing Computer hardware
283	Who Cares About the Memory Hierarchy? CS252 Graduate Computer Architecture Lecture 4 Add to Reading List Source URL: www.cs.berkeley.edu Language: English - Date: 2003-06-11 14:31:47 Cache Central processing unit CPU cache Alpha 21164 Memory hierarchy Dynamic random-access memory Compiler optimization Write buffer Cache algorithms Computer memory Computer hardware Computing
284	An FPGA architecture for DRAM-based systolic computations Norman Margolus Boston University Center for Computational Science and MIT Artificial Intelligence Laboratory Abstract Add to Reading List Source URL: people.csail.mit.edu Language: English - Date: 2005-01-16 13:05:57 Computer architecture Central processing unit Dynamic random-access memory Digital electronics Field-programmable gate array Cell Parallel computing Microprocessor CPU cache Computer hardware Computer memory Electronic engineering
285	To appear in Proceedings of the 1994 IEEE Computer Conference, San Francisco. Copyright © 1994 IEEE Low Power Hardware for a High Performance PDA Michael Culbert, Add to Reading List Source URL: waltersmith.us Language: English - Date: 2012-05-07 17:56:07 Computer architecture MessagePad Newton Multi-core processor ARM architecture CPU cache Acorn Computers Translation lookaside buffer Memory management unit Computing Computer hardware Apple Newton
286	Late-Binding: Enabling Unordered Load-Store Queues Franziska Roesner x Simha Sethumadhavan x y x Joel S. Emer Add to Reading List Source URL: www.franziroesner.com Language: English - Date: 2009-10-21 14:03:34 Central processing unit Memory disambiguation CPU cache Microarchitecture Hazard Branch predictor Processor register Out-of-order execution DEC Alpha Computer architecture Computer hardware Computer engineering
287	Architectural Support for Parallel Reductions in Scalable Shared-Memory Multiprocessors Add to Reading List Source URL: research.ac.upc.edu Language: English - Date: 2002-03-20 08:48:05 Parallel computing CPU cache Cache Computer memory Speedup Automatic parallelization Computing Central processing unit Computer hardware
288	Appears in the Proceedings of the 35th Annual International Symposium on Computer Architecture Counting Dependence Predictors Franziska Roesner Doug Burger Add to Reading List Source URL: www.franziroesner.com Language: English - Date: 2009-10-21 14:03:38 Memory dependence prediction Memory disambiguation Branch predictor CPU cache Alpha 21264 Microarchitecture Structural load Central processing unit Explicit Data Graph Execution Computer architecture Computer engineering Computer hardware
289	1. Introduction The purpose of this paper is two fold. The first part gives an overview of cache, while the second part explains how the Pentium Processor implements cache. A simplified model of a cache system will be ex Add to Reading List Source URL: download.intel.com Language: English - Date: 2006-12-19 16:48:38 Cache coherency Cache Central processing unit CPU cache MESI protocol Pentium Pro Bus sniffing Dynamic random-access memory Cache on a stick Computer hardware Computer memory Computing
290	R ET C ON: Transactional Repair without Replay Colin Blundell Arun Raghavan Milo M. K. Martin Add to Reading List Source URL: www.cis.upenn.edu Language: English - Date: 2010-04-10 11:24:17 Data Transaction processing Abstract interpretation Symbolic execution MIX Hash table ATS CPU cache Extensible Storage Engine Computing Computer memory Computer programming

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